The present invention relates generally to integrated circuit debugging systems, and more specifically to a system which combines the use of an electron beam probe and a photon beam probe.
Generally, the industry of semiconductor manufacturing involves highly complex techniques for integrating circuits into semiconductor materials. Due to the large scale of circuit integration and the decreasing size of semiconductor devices, the semiconductor manufacturing process is prone to processing defects. Testing procedures are therefore critical to maintain quality control. Since the testing procedures are an integral and significant part of the manufacturing process, the semiconductor industry constantly seeks more efficient testing procedures so that the entire manufacturing process may be improved.
Currently, electron beam scanning and photon beam scanning are two techniques that are sometimes used to test semiconductor devices. Electron beam scanning may be used to scan and test the metal trace layers of the semiconductor devices. Typically, electron beam scanning is performed from the front side of the devices. Photon beam scanning may be used to scan and test the diffusion areas embedded within the semiconductor material. Typically, photon beam scanning is performed from the backside of the devices. Both electron beam and photon beam scanning techniques are important for debugging the metal trace layers and the diffusion areas of integrated circuits in the semiconductor industry. Unfortunately, however, to perform both of these testing techniques, separate machines and facilities, and unique procedures for preparing for each test are necessary. The unique requirements for each technique present time and cost inefficiencies. Therefore, it would be desirable to develop a testing system, which uses both electron beam and photon beam scanning techniques, that is capable of testing semiconductor devices in an efficient and effective manner.
The present invention presents an efficient and effective testing system which uses both electron beam and photon beam scanning techniques to scan and test semiconductor devices. The testing system of the present invention includes an electron beam probe, a photon beam probe, and a device under test (DUT) card holder which is positioned between the electron beam probe and the photon beam probe. The DUT card holder secures and positions a DUT card, which includes a device under test (DUT), during the operation of the test system. The electron beam probe and the photon beam probe each direct a beam of energy onto a first and second side of an IC device under test, respectively. A first valve is positioned between the electron beam probe and the DUT. A second valve, located on an opposite side of the DUT from the first valve, is positioned between the photon beam probe and the DUT. The first and second valve operate in cooperation to control the pressure surrounding the DUT card. One embodiment of the invention includes a first test chamber and a second test chamber. The first test chamber includes the area between the first side of the DUT card and the first valve. The second test chamber includes the area between the second side of the DUT card and the second valve. Time and cost savings are obtained by combining electron and photon beam probing capabilities into a single test system because the implementation of two separate probing systems is avoided.
Another aspect of the present invention is directed at a method for using the test system of the present invention to scan and test a first and a second surface of a semiconductor device. To facilitate electron beam probing, the DUT is isolated from the photon probe so that a vacuum pressure may be created within the first and second test chamber. After the vacuum pressure has been established, a first surface of the DUT is scanned with the electron beam. To facilitate photon probing, the DUT is isolated from the electron beam probe and exposed to the photon beam probe so that the second surface of the DUT may be scanned with the photon beam.
In another aspect, a method for preparing a packaged integrated circuit (IC) for testing by the testing system of the present invention is described. The preparation method involves preparing a first and a second surface of a packaged IC since the testing system will scan a first surface with an electron beam probe and a second surface with a photon beam probe. The preparation method includes removing packaging material from the first and second surfaces of a packaged IC as necessary, etching passivation material away from the first surface of the IC, and thinning the second surface of the IC.
In yet another aspect of the present invention, a DUT card which secures and positions the DUT for testing within the testing system is described. The DUT card includes a socket which is attached to a circuit card. The socket and circuit card both have openings which are aligned with each other. A DUT is secured by the socket opening such that both a first and a second surface of the DUT are accessible to beam probes through the socket and circuit card openings. In one embodiment of the present invention, the DUT card includes a locking mechanism capable of locking the DUT within the socket.
These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures which illustrate by way of example the principles of the invention.